In order to read a memory in which data for generating a digital data stream is stored, a series of addresses must be provided to the memory in the order in which the individual data elements representing the digital data stream are stored in the memory. Generation of such a digital data stream is necessary, for example, for generating a logic pattern for logic circuit testing or for generating an arbitrary waveform for analog (or analog-digital mixed) circuit testing.
In recent years, the operating speeds and complexity of the devices under test such as ICs have grown, the frequencies needed for testing signals has become higher, and longer test patterns have become required for this type of testing. Therefore, it has also been necessary to speed up the available data rate and to increase the amount of data associated with the testing signals.
One simple technique for satisfying the above requirements might be to use a high-speed and large capacity memory for generating the digital data streams. However, memory elements having an extremely short access time are typically unavailable. Even if available, an attempt to increase the capacity would increase the cost, heat generated, mounting area, and the like to an unacceptable level.
To solve the above problem, a memory interleaving scheme is usually employed. In this scheme, a plurality of mutually independently operating memory banks (usually, a power of 2 number of memory banks, such as 2, 4, 8, etc.) are provided, and addresses are assigned to the respective memory banks in a manner of traversing around these memory banks in sequence so that successive addresses are not assigned to any one memory bank. For example, in a two-way interleaving scheme in which two memory banks are used, even and odd addresses are assigned to banks "0" and "1" respectively so that accesses to any consecutive addresses are distributed to banks "0" and "1" in an alternating manner. In this case, the access time of each memory bank is allowed to be as long as twice the access time required for the entire memory system insofar as alternating accessing is carried out. Likewise, the access times of four times and eight times are allowed in four-way and eight-way interleaving schemes respectively. Therefore, a high-speed memory system can be constructed using memory elements of a slow access time, but low cost, high capacity, low power dissipation as well as high availability.
However, during the generation of a digital data stream to be used for generation of the testing signal, it is not usually allowed to insert a wait cycle within the data stream for the convenience of the memory. Therefore, there exist some sequences of data which cannot be generated using the memory interleaving scheme as described above.
For example, with the memory employing the two-way interleaving exemplified as above, the data stream which requires the reading sequence indicated below cannot be generated without inserting wait cycles therein: the address sequence is 0.fwdarw.1.fwdarw.2.fwdarw.0.fwdarw.1.fwdarw.2.fwdarw.0.fwdarw.1.fwdarw.2. fwdarw.3.fwdarw.. . .
This is problematic since it is necessary to read from address 0 immediately after reading from address 2, in which case it is needed to make successive accesses to the memory bank to which the even addresses are assigned (memory bank 0).
Therefore, when employing the interleaving scheme described above, there remains a restriction on the data streams that can be generated.